Programmable logic devices (PLDs) exist as a well-known type of integrated circuit (IC) that may be programmed by a user to perform specified logic functions. There are different types of programmable logic devices, such as programmable logic arrays (PLAs) and complex programmable logic devices (CPLDs). One type of programmable logic device, known as a field programmable gate array (FPGA), is very popular because of a superior combination of capacity, flexibility, time-to-market, and cost.
An FPGA typically includes an array of configurable logic blocks (CLBs), programmable input/output blocks (IOBs), and like type programmable elements. The CLBs and IOBs are interconnected by a programmable interconnect structure. The programmable logic of an FPGA (e.g., CLBs, IOBs, and interconnect structure) is typically programmed by loading a stream of configuration data (known as a bitstream) into internal configuration memory cells. The bitstream is typically stored in an external nonvolatile memory, such as an erasable programmable read only memory (EPROM). The states of the configuration memory cells define how the CLBs, IOBs, interconnect structure, and other programmable logic are configured. Some FPGAs allow for dynamic, partial reconfiguration while active.
An FPGA may also include various dedicated logic circuits as programmable elements among the CLBs and IOBs (referred to as hardware blocks). Such hardware blocks include memories, digital clock managers (DCMs), and input/output (I/O) transceivers, embedded processors, digital signal processors (DSPs), multipliers, and the like. Notably, some hardware blocks include internal registers that are less accessible that other registers in the PLD (e.g., registers in a CLB). For example, a hardware block may include internal registers that cannot be independently set or read back during partial reconfiguration of the PLD (whereas registers in a CLB, for example, can be set and read back during partial reconfiguration). Moreover, the state of some internal registers in a hardware block may always be zero in response to a synchronous reset. Examples of such internal registers include pipeline registers in DSP and multiplier hardware blocks.
The reduced accessibility of internal registers in a hardware block may prevent certain use scenarios and can increase design area. Presently, if a user desires to initialize internal registers, the design requires insertion of extra registers in the data path of the hardware block that are capable of being initialized. Furthermore, the reduced accessibility of internal registers in a hardware block may reduce circuit throughput (e.g., if initializable registers are inserted in a feedback loop). Accordingly, there exists a need in the art for a method and apparatus for accessing at least one internal register of a hardware block in a PLD that overcomes the aforementioned deficiencies.